LEPD Octal Serial Solenoid Driver. EIGHT LOW RDSon DMOS OUTPUTS @ 25°C VCC 5%) 8 BIT SERIAL INPUT DATA (SPI) 8 BIT SERIAL DIAGNOSTIC . LEPD datasheet, LEPD circuit, LEPD data sheet: STMICROELECTRONICS – Octal serial solenoid driver,alldatasheet, datasheet, Datasheet. LEPD datasheet, LEPD circuit, LEPD data sheet: STMICROELECTRONICS – OCTAL SERIAL SOLENOID DRIVER,alldatasheet, datasheet.
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Byte Timing with Asynchronous Reset. Page 13 LE Figure 6. Page 7 LE 2. At the rising edge of CE the shift register data is latched into the parallel latch and the output stages will be actuated by the new data. Page 12 Functional description 4. LEPD datasheet and specification datasheet Download datasheet.
Status monitor function is available on all output. Revision history 6 Revision history Table 6. Each output has a current limit circuit which limits the maximum output current to at least 1. Copy your embed code and put on your site: Page 4 List of figures List of figures Figure 1. I LE Changes characteristics, the max. Clock in the same control byte and observe the diag- nostic data that comes out of the device.
Download datasheet Kb Share this page. Page 9 LE Table 5. Multiwatt 15 mechanical data and package dimensions DIM. All other trademarks are the property of their respective owners. Wait microseconds or so to allow the outputs to settle.
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LEPD Datasheet – OCTAL SERIAL SOLENOID DRIVER from SGS-Thomson Microelectronics
Page 2 Contents Contents 1 Block diagram. This allows the part to overcome any high inrush cur. LEPD datasheet and specification datasheet. The diag- nostic bits should be dataeheet to the bits that were first clocked in. Page 16 Revision history 6 Revision history Table 6. Page 15 LE Figure 8.
OCTAL SERIAL SOLENOID DRIVER
List of figures List of figures Figure 1. Each channel is independently controlled by an output latch and a common Any differences would point to a fault on that output. Pin description 2 Pin description Figure 2. Contents Contents 1 Block diagram. Page 8 Electrical specifications 3 Electrical specifications 3. Clock in the same control byte and observe the diag. Page 11 LE 4. Clock in a new control byte.
If the output was programmed OFF by clocking in a one, and a zero came back as the diagnostic bit for that output, nothing had pulled the output pin high and it must be floating, so an open circuit condition exists for that output.
Clock in a new control byte. Any differences would point to a fault.
PowerSO pin connection top view Figure 3. Page 5 LE 1 Block diagram Figure datasyeet. Clock in the same control byte This allows the part to overcome any high inrush cur- rents that may flow immediately after turn on.
LE List of tables Table 1. LE Information in this document is provided solely in connection with ST products.
LE 1 Block diagram Figure 1. The SCLK input is gated by the. Checking for fault conditions may be done in the fol. Once the delay period has elapsed, the output voltages are sensed by the comparators and any output with voltages higher than 1.
Page 3 LE List of tables Table 1. If the output was programmed ON by clocking in a zero, l9822epx a one came back as the di- agnostic bit for that output, the output pin was still high and a short circuit or overload condition exists. Data is transmitted serially to the device using the. Electrical specifications 3 Electrical specifications datasheett.
Page 6 Pin description 2 Pin description Figure 2.